In such a system it is known, e.g. from U.S. Pat. No. 3,110,853, to provide a reversible counter which is stepped in one sense (e.g. additively) by reference pulses of fixed frequency and in the opposite sense (e.g. subtractively) by monitoring pulses which are generated in predetermined angular positions of the motor shaft and whose cadence is therefore proportional to the actual motor speed. The term "actual motor speed" is here used to distinguish from the rated speed of the motor which is represented by the recurrence frequency or cadence of the reference pulses and from which the actual speed should deviate as little as possible. A coarse control of the motor speed is carried out with the aid of analog signal derived from a frequency comparator directly receiving the two pulse trains; a fine control is achieved, for actual motor speeds close to the rated speed, through a decoder which converts the reading of the reversible counter into a phasing signal in analog form indicative of either a positive or a negative count. The aforementioned patent also describes an anticoincidence circuit designed to prevent counting errors due to the overlapping of pulses appearing more or less simultaneously at the additive and subtractive inputs of the counter.
The coarse speed control based on frequency differences of the two pulse trains often leads to overcorrection, causing the system to hunt about the rated speed value between limits depending on the sensitivity of the frequency comparator. Because of the generally low power of resolution of such frequency comparators, the speed excursions occur within a wide range.